1. Field of the Invention
This invention relates to data buffers and to data storage or processing apparatus comprising one or more data buffers.
2. Description of the Prior Art
Data that has been retrieved from a storage medium or which is to be transmitted in some way often has to be "buffered" or temporarily stored in an electronic memory. Commonly, a "first-in-first-out" (FIFO) memory is used for this purpose, so that the buffered data is read out in the order in which it was received by the buffer memory.
One previously proposed type of FIFO is a dual-port memory having a read pointer and a write pointer that rotate through the memory as data is written in or read out. An example of this type of FIFO is the NEC UPD42280GU-30 integrated circuit FIFO memory.
However, a feature of this FIFO design is that the read pointer and the write pointer must never be allowed to meet (i.e. to point to the same address within the memory), or even to come within a minimum addressing offset of, say, 200 bytes. If the pointers do meet, data can be lost.
The pointers could meet if all of the buffered data in the FIFO was read out before more data was written into the FIFO. This could happen if there is a delay in the data retrieval or processing which loads data into the FIFO.
One way of avoiding the possibility of the read and write pointers meeting in normal operation is to use a larger FIFO and to buffer a larger amount of data than would otherwise be necessary. However, this requires more hardware (i.e. the larger FIFO itself) and, more importantly, imposes a greater delay on the data being buffered because (a) the data may be held for a longer time in the FIFO; and (b) more data has to be loaded into the FIFO before the buffered data can start to be read out.